This invention relates to a semiconductor memory device, and more particularly to a sense amplifier of a nonvolatile semiconductor memory using current read-out type memory cells.
FIG. 1 shows a circuit arrangement of the read-out system of a conventional nonvolatile semiconductor memory represented by a NOR-EEPROM. In a DRAM made up of charge read-out type memory cells, a flip-flop type sense amplifier is used. In an EEPROM, however, which is made up of current read-out type memory cells, a differentially amplifying sense amplifier as shown in FIG. 1. This sense amplifier circuit is taught in IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 1, pp. 422-7, February 1985.
The sense amplifier 3 is an operational amplifier OP having two input terminals, and these input terminals are connected to a sense node SA and a reference node REF, respectively.
The sense node SA is connected to a data line DL through a clamping NMOS transistor QN1. Connected to the data line DL is a bit line BL of a memory cell array 1 selected by an NMOS transistor QN3 of a column gate 2. Between the sense node SA and the power source terminal, a PMOS transistor QP1 with connected gate and drain is provided as a current source load.
Connected to the reference node REF is a PMOS transistor QP2 as a current source load similarly to the sense node SA. Also connected to the reference node REF is a dummy data line RDL through a clamping NMOS transistor QN2 like the sense node SA. Connected to the dummy data line RDL is a dummy cell RMC via an NMOS transistor QN4 of a dummy column gate. These PMOS transistor QP2, clamping NMOS transistor QN2, dummy column gate transistor QN4 and dummy cell RMC on the part of the reference node REF form a reference voltage generating circuit 4. The reference voltage generating circuit 4 is configured to generate a reference voltage in an intermediate level of output voltage corresponding to two-valued data obtained at the sense node SA.
The PMOS transistor QPl as the current source load has a conductance much smaller than that of the clamping NMOS transistor
QN1, and its gate and drain are connected for pentode operation. This is for the purpose of diminishing voltage changes of the data line DL to a very small amplitude and applying it to the sense node SA. The clamping NMOS transistor QN1 and the power source PMOS transistor QP1 make up an initial stage amplifier. The voltage amplified by the initial stage amplifier is compared and further amplified by the operational amplifier OP, and a sense output SAOUT in the CMOS level is obtained.
FIG. 2 shows a conventional sense amplifier modified from the circuit arrangement of FIG. 1. This circuit system is disclosed in IEEE Journal of Solid-State Circuits Conference Digest of Technical Papers, pp. 146-7, February 1994. In the circuit of FIG. 1, a fixed bias voltage BIAS is applied to gates of the clamping NMOS transistors QN1 and QN2. In contrast, in FIG. 2, voltages of the data line DL and the dummy data line RDL are fed back to gates of the NMOS transistors QN1 and QN2 via inverters I1 and I2, respectively. By feedback control of the conductivity of the clamping NMOS transistor QN1 in this manner, voltages corresponding to two-valued data can be applied to the sense node SA while suppressing the voltage amplitude of the data line DL.
Although miniaturization of EEPROM memory cells have progressed and source voltages have also been lowered to about 3V, a further decrease of power source voltages to about 2V, for example, is demanded. However, for realization of a 2V source, problems arise in the conventional sense amplifier circuit arrangements of FIG. 1 and FIG. 2. That is, for reliably detecting whether a current is pulled into a memory cell or not, at least 1V, approximately, is required as the charge level of the bit line BL. Further, in the sense amplifier circuit shown in FIG. 1 and FIG. 2, the PMOS transistor QP1 as the current source load and the clamping NMOS transistor QN1 enter in series between the power source terminal and the data line DL. Expressing the threshold voltage of the PMOS transistor QP1 as Vthp, if |Vthp|=0.8 V, approximately, the PMOS transistor QP1 needs at least 0.8V, i.e. 1V, for example, as its source-drain voltage in order to function as a current source. Additionally, in order to operate the clamping NMOS transistor QN1 in the pentode operation region, 0.2 through 0.3V is required as its drain-source voltage. Therefore, if the power source voltage is reduced to 2V, the necessary bit line charge level of 1V is not obtained.
It is therefore an object of the invention to provide a semiconductor memory device using a sense amplifier circuit which enables a decrease of the power source voltage.
According to a first aspect of the invention, there is provided
a semiconductor memory device comprising:
a memory cell array in which bit lines and word lines are arranged to cross and current read-out type memory cells are arranged at crossing points thereof;
a decoding circuit for selecting a bit line and a word line of said memory cell array;
a plurality of sense amplifiers for detecting and amplifying data read out onto bit lines selected from a plurality of bit lines provided for a predetermined number of bit lines, said sense amplifiers being provided for every I/O lines of said memory cell array, said sense amplifier having a sense node as one input terminal and a reference node as the other input terminal; and
a reference voltage generator circuit for providing a reference voltage having a level between voltages of two-valued data output to said sense node;
wherein said sense node of each sense amplifier is connected to corresponding I/O line and said reference node of each sense amplifiers is commonly connected to said reference voltage generator.
By removing a clamping circuit conventionally used in a sense amplifier circuit, the invention makes it possible to lower the power source voltage as compared with conventional techniques, have the current source load transistor operate in a pentode mode even when using a 2V power source, and ensure about 1V as the charge level of bit lines to enable normal data read operation.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array in which bit lines and word lines are arranged to cross and current read-out type memory cells are arranged at crossing points thereof;
a decoding circuit for selecting a bit line and a word line of said memory cell array;
a selection gate for selecting a plurality of bit lines of said memory cell array simultaneously; and
the same number of sense amplifiers as the number of said bit lines, which individually detect and amplify data read out onto said bit lines simultaneously selected by said selection gate,
each of said sense amplifiers including:
at least one stage of operational amplifier having a sense node connected to a selected bit line of said memory cell array as one of input terminals thereof and a reference node shared by said plurality of sense amplifiers as the other of said input terminals;
a first current source load interposed between said sense node and a power source terminal for each operational amplifier;
a second current source load interposed between said reference node and said power source terminal; and
a reference voltage generating circuit connected to said reference node to generate a reference voltage of a level between voltages of two-valued data output to said sense node.
Moreover, in case of using a plurality of sense amplifiers simultaneously executing data reading, these sense amplifiers share a common reference node, and first and second current source loads are provided for the sense node and the reference node in each sense amplifier. Then, in the reference node, a reference voltage generating circuit for generating a reference voltage between voltages of two-valued data output to the sense node is provided to be shared by a plurality of sense amplifiers. Thereby, reliable data reading operation is possible even when the power source voltage is lowered.